Photolithography is used in the manufacture of integrated circuits to form the very small structures required by such circuits. A typical photolithographic process involves the patterning of a photosensitive layer called photoresist to form a patterned mask. The patterned mask is then used to define the underlying layers. In integrated circuits that comprise metal oxide semiconductor (MOS) transistors the most critical dimension is often the length of the MOS transistor gate structure. The length of the MOS transistor gate greatly affects the performance of the transistor and, as such, the length must be very tightly controlled during manufacture.
In forming a MOS transistor gate structure, a blanket layer of the material that will be used to form the transistor gate is first formed on the MOS transistor gate dielectric. Given the constraints of current lithographic processes a bottom anti-reflective layer (BARC) is formed on the blanket layer before the formation of the photoresist that will be used to pattern the MOS transistor gate. Following the patterning of the photoresist layer which is formed on the BARC layer, the BARC layer is patterned by etching the BARC layer using the overlying patterned photoresist layer as an etch mask. Following the patterning of the BARC layer and before the etching of the blanket layer of the transistor gate layer, the BARC dimensions are adjusted by performing an over-etch of the BARC layer. Such an over-etch process will change the dimensions of the patterns in the BARC layer allowing the formation of MOS transistor gate structures with the desired dimensions. The determination of the required BARC over-etch time is critical to obtaining tightly controlled MOS transistor gate lengths. Integrated circuits are usually formed in batches of wafers called lots. A typical lot size comprises about 25 wafers. Current methods of determining the BARC over-etch time often results in wide fluctuations in MOS transistor gate lengths from wafer to wafer within a lot. There is therefore a great need for a method to determine the required BARC over-etch times that reduce the fluctuations in MOS transistor gate length for all wafers within a lot. The instant invention addresses this need.